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<title>VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word </title></head>
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<h1>VPMOVQW/VPMOVSQW/VPMOVUSQW—Down Convert QWord to Word</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.128.F3.0F38.W0 34 /<em>r</em></p>
<p>VPMOVQW <em>xmm1/m32 {k1}{z}, xmm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Converts 2 packed quad-word integers from <em>xmm2 </em>into 2 packed word integers in <em>xmm1/m32 </em>with truncation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.128.F3.0F38.W0 24 /<em>r</em></p>
<p>VPMOVSQW <em>xmm1/m32 {k1}{z}, xmm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Converts 8 packed signed quad-word integers from <em>zmm2</em> into 8 packed signed word integers in <em>xmm1/m32 </em>using<em> </em>signed saturation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.128.F3.0F38.W0 14 /<em>r</em></p>
<p>VPMOVUSQW <em>xmm1/m32 {k1}{z}, xmm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Converts 2 packed unsigned quad-word integers from <em>xmm2</em> into 2 packed unsigned word integers in <em>xmm1/m32 </em>using<em> </em>unsigned saturation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.F3.0F38.W0 34 /<em>r</em></p>
<p>VPMOVQW <em>xmm1/m64 {k1}{z}, ymm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Converts 4 packed quad-word integers from <em>ymm2 </em>into 4 packed word integers in <em>xmm1/m64 </em>with truncation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.F3.0F38.W0 24 /<em>r</em></p>
<p>VPMOVSQW <em>xmm1/m64 {k1}{z}, ymm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Converts 4 packed signed quad-word integers from <em>ymm2</em> into 4 packed signed word integers in <em>xmm1/m64 </em>using<em> </em>signed saturation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.256.F3.0F38.W0 14 /<em>r</em></p>
<p>VPMOVUSQW <em>xmm1/m64 {k1}{z}, ymm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>
<p>AVX512VL</p>
<p>AVX512F</p></td>
<td>Converts 4 packed unsigned quad-word integers from <em>ymm2</em> into 4 packed unsigned word integers in <em>xmm1/m64 </em>using<em> </em>unsigned saturation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.F3.0F38.W0 34 /<em>r</em></p>
<p>VPMOVQW <em>xmm1/m128 {k1}{z}, zmm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Converts 8 packed quad-word integers from <em>zmm2 </em>into 8 packed word integers in <em>xmm1/m128 </em>with truncation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.F3.0F38.W0 24 /<em>r</em></p>
<p>VPMOVSQW <em>xmm1/m128 {k1}{z}, zmm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Converts 8 packed signed quad-word integers from <em>zmm2</em> into 8 packed signed word integers in <em>xmm1/m128 </em>using<em> </em>signed saturation under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.512.F3.0F38.W0 14 /<em>r</em></p>
<p>VPMOVUSQW <em>xmm1/m128 {k1}{z}, zmm2</em></p></td>
<td>QVM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Converts 8 packed unsigned quad-word integers from <em>zmm2</em> into 8 packed unsigned word integers in <em>xmm1/m128 </em>using<em> </em>unsigned saturation under writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>QVM</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed words using truncation. VPMOVSQW converts signed 64-bit integers into packed signed words using signed saturation. VPMOVUSQW convert unsigned quad-word values into unsigned word values using unsigned saturation.</p>
<p>The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit memory location.</p>
<p>Down-converted word elements are written to the destination operand (the first operand) from the least-significant word. Word elements of the destination operand are updated according to the writemask. Bits (MAX_VL-1:128/64/32) of the register destination are zeroed.</p>
<p>EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.</p>
<p><strong>Operation</strong></p>
<p><strong>VPMOVQW instruction (EVEX encoded versions) when dest is a register</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 16</p>
<p>m (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+15:i] (cid:197) TruncateQuadWordToWord (SRC[m+63:m])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+15:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>DEST[i+15:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL/4] (cid:197) 0;</p>
<p><strong>VPMOVQW instruction (EVEX encoded versions) when dest is memory</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 16</p>
<p>m (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+15:i] (cid:197) TruncateQuadWordToWord (SRC[m+63:m])</p>
<p>ELSE</p>
<p>*DEST[i+15:i] remains unchanged*</p>
<p>; merging-masking</p>
<p>FI;</p>
<p>ENDFOR</p>
<p><strong>VPMOVSQW instruction (EVEX encoded versions) when dest is a register</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 16</p>
<p>m (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+15:i] (cid:197) SaturateSignedQuadWordToWord (SRC[m+63:m])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+15:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>DEST[i+15:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL/4] (cid:197) 0;</p>
<p><strong>VPMOVSQW instruction (EVEX encoded versions) when dest is memory</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 16</p>
<p>m (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+15:i] (cid:197) SaturateSignedQuadWordToWord (SRC[m+63:m])</p>
<p>ELSE</p>
<p>*DEST[i+15:i] remains unchanged*</p>
<p>; merging-masking</p>
<p>FI;</p>
<p>ENDFOR</p>
<p><strong>VPMOVUSQW instruction (EVEX encoded versions) when dest is a register</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 16</p>
<p>m (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+15:i] (cid:197) SaturateUnsignedQuadWordToWord (SRC[m+63:m])</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+15:i] remains unchanged*</p>
<p>ELSE *zeroing-masking*</p>
<p>; zeroing-masking</p>
<p>DEST[i+15:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL/4] (cid:197) 0;</p>
<p><strong>VPMOVUSQW instruction (EVEX encoded versions) when dest is memory</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 16</p>
<p>m (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+15:i] (cid:197) SaturateUnsignedQuadWordToWord (SRC[m+63:m])</p>
<p>ELSE</p>
<p>*DEST[i+15:i] remains unchanged*</p>
<p>; merging-masking</p>
<p>FI;</p>
<p>ENDFOR</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalents</strong></p>
<p>VPMOVQW __m128i _mm512_cvtepi64_epi16( __m512i a);</p>
<p>VPMOVQW __m128i _mm512_mask_cvtepi64_epi16(__m128i s, __mmask8 k, __m512i a);</p>
<p>VPMOVQW __m128i _mm512_maskz_cvtepi64_epi16( __mmask8 k, __m512i a);</p>
<p>VPMOVQW void _mm512_mask_cvtepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);</p>
<p>VPMOVSQW __m128i _mm512_cvtsepi64_epi16( __m512i a);</p>
<p>VPMOVSQW __m128i _mm512_mask_cvtsepi64_epi16(__m128i s, __mmask8 k, __m512i a);</p>
<p>VPMOVSQW __m128i _mm512_maskz_cvtsepi64_epi16( __mmask8 k, __m512i a);</p>
<p>VPMOVSQW void _mm512_mask_cvtsepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);</p>
<p>VPMOVUSQW __m128i _mm512_cvtusepi64_epi16( __m512i a);</p>
<p>VPMOVUSQW __m128i _mm512_mask_cvtusepi64_epi16(__m128i s, __mmask8 k, __m512i a);</p>
<p>VPMOVUSQW __m128i _mm512_maskz_cvtusepi64_epi16( __mmask8 k, __m512i a);</p>
<p>VPMOVUSQW void _mm512_mask_cvtusepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);</p>
<p>VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);</p>
<p>VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);</p>
<p>VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);</p>
<p>VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);</p>
<p>VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);</p>
<p>VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);</p>
<p>VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);</p>
<p>VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);</p>
<p>VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);</p>
<p>VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);</p>
<p>VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);</p>
<p>VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);</p>
<p>VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);</p>
<p>VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);</p>
<p>VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);</p>
<p>VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);</p>
<p>VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);</p>
<p>VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);</p>
<p>VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);</p>
<p>VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);</p>
<p>VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);</p>
<p>VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);</p>
<p>VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);</p>
<p>VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<table>
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E6.</td></tr>
<tr>
<td>If EVEX.vvvv != 1111B.</td></tr></table></body></html>